December 17, 2011

DIGITAL IC APPLICATIONS JNTU previous years question papers

Time: 3 hours Max Marks: 80

Answer any FIVE Questions

All Questions carry equal marks

1. (a) Draw the CMOS circuit diagram of tri-state buffer. Explain the circuit with the help of logic diagram and function table.
(b) Design a CMOS transistor circuit that has the functional behavior as
f(a) = (P + Q). (Q + R)
Also explain its functional operation. [8+8]

2. (a) Draw the circuit diagram of a two-input LS-TTL NOR gate and explain itsfunctional behavior?
(b) Mention the DC noise margin levels of ECL logic family. [10+6]

3. (a) Explain with an example the syntax and the function of the following VHDL statements:
i. Process Statement
ii. Case Statement
(b) Explain Implicit and Explicit visibility of a Library in VHDL? [8+8]

4. (a) Explain data-flow design elements of VHDL.
(b) Design the logic circuit and write a structural style VHDL program for the following function. [8+8]
F(A) = p,q,r,s (1, 3, 4, 5, 6, 7, 9, 12, 13, 14)

5. Draw the logic diagram of 74×283 IC and explain its operation. Write data flow VHDL program for this IC. [16]

6. Write VHDL program for 1-bit comparator circuit with the input bits and equal, greater than and less than inputs from the previous stage and the outputs contain equal, greater than and less than conditions. Using this entity write VHDL program for 16-bit comparator using data flow style. Do not use any additional logic for this purpose. [16]

7. (a) Design a 4-bit binary synchronous counter using 74×74. Write VHDL program for this logic. Using data flow style.
(b) Design a modulo-60 counter using 74×163 Ics.

8. (a) How many ROM bits are required to build a 16-bit adder/subtractor with mode control, carry input, carry output and two?s complement overflow output? Show the block schematic with all inputs and outputs?
(b) Design an 8×4 diode ROM using 74×138 for the following data starting from the first location. [8+8]
B, 2, 4, F, A,D, F,E



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