DIGITAL DESIGN THROUGH VERILOG ECE JNTU previous years question papers

Time: 3 hours

Max Marks: 80

Answer any FIVE Questions

All Questions carry equal marks

1. (a) Design a JK flip flop using NAND gates.
(b) Write a verilog code for JK flip flop using NAND gates.[8+8]

2. (a) Explain module with an example using verilog code?
(b) Explain port Declaration with an example using verilog code?[8+8]

3. (a) Explain edge sensitive path using an example.
(b) Explain over riding parameters.[8+8]

4. Explain UART Transmission with SM Chart. [16]

5. (a) Explain NMOS enhancement with conditions.
(b) Write about Basic switch primitives.[8+8]

6. Explain parallel adder-subtractor with logic cell. [16]

7. (a) Write a verilog module for a rudimentary serial transmitter module.
(b) Explain Multiple Always Blocks.[8+8]

8. (a) Construct an PLA and D-flip flop equivalent to the following state table. Test only one variable in each decision box. Try to minimize the number of decision boxes.
(b) Write a VHDL description of the state machine based on the PLA and D-flip flop. [8+8]

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