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VLSI DESIGN JNTU previous years question papers
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
1. Distinguish between thin film resistors and thin film capacitors in all aspects. 
2. (a) Derive an equation for Ids of an n channel enhancement MOSFET operating
in saturation region.
(b) An n MOS transistor is operating in saturation region with the following
parameters.Vgs=5V, Vtn =1.2V, (W/L) =10: µncox=110µA/V 2. Find transcon-
ductance of the device. [8+8]
3. (a) Discuss the rule for n well and VDD and Vss contacts (2µm CMOS).
(b) Discuss the rule for pad and over glass geometry (2µm CMOS). [8+8]
4. Calculate on resistance of the circuit from VDD to GND. If
n- channel sheet resistance Rsn=104
per square and P-channel sheet resistance
Rsp = 3.5 × 104
5. Draw the logic diagram for a ripple-carry binary counter using T registers and ex-
plain its operation with the help of truth table and also compare it with synchronous
counters. Draw the schematic for T register. 
6. (a) Draw the typical architecture of PAL and explain the operation of it.
(b) What is CPLD? Draw its basic structure and give its applications.
7. (a) Explain how a FSM model is described in VHDL with suitable program.
(b) What is the difference between Design capture tools and design verification
tools? Give some examples of each. [8+8]
8. (a) Explain the gate level and function level of testing.
(b) A sequential circuit with in? inputs and ‘m’ storage devices. To test this
circuit how many test vectors are required.
(c) What is sequential fault grading? Explain how it is analyzed.