December 17, 2011

SWITCHING THEORY AND LOGIC DESIGN JNTU previous years question papers

SWITCHING THEORY AND LOGIC DESIGN JNTU previous years question papers

Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks

1. (a) What is the Gray code? What are the rules to construct Gray code? Develop the 4 bit Gray code for the decimal 0 to 15.
(b) List the XS3 code for decimal 0 to 9.
(c) What are the rules for XS3 addition? Add the two decimal numbers 123 and 658 in XS3 code. [8+2+6]

2. (a) State Duality theorem. List Boolean laws and their Duals.
(b) Simplify the following Boolean functions to minimum number of literals:
i. F = ABC + ABC’ + A’B
ii. F = (A+B)’ (A’+B’).
(c) Realize XOR gate using minimum number of NAND gates. [8+4+4]

3. Simplify the following Boolean expressions using K-map and implement them using NOR gates:
(a) F (A, B, C, D) = AB’C’ + AC + A’CD’
(b) F (W, X, Y, Z) = W’X’Y’Z’ + WXY’Z’ + W’X’YZ + WXYZ. [16]

4. (a) Design BCD to Gray code converter and realize using logic gates.
(b) Design 2*4 decoder using NAND gates. [10+6]

5. (a) Draw the basic macro cell logic diagram and explain.
(b) Explain the general CPLD configuration with suitable block diagram. [16]

6. (a) Draw the logic diagram of a 4 bit binary ripple counter using positive edge triggering.
(b) Draw the block diagram of a 4 - bit serial adder and explain its operation.[16]

7. (a) Write the differences between Mealy and Moore type machines.
(b) A sequential circuit has 2 inputs w1=w2 and an output z. It’s function is to compare the i/p sequence on the two i/p’s. If w1=w2 during any four consecutive clock cycles, the circuit produces z=1 otherwise
w1= 0110111000110
w2= 1110101000111

8. (a) For the given control state diagram obtain its equivalent ASM chart.
(b) Design control logic circuit using multiplexers.



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