MICROPROCESSORS AND INTERFACING JNTU previous years question papers

MICROPROCESSORS AND INTERFACING JNTU previous years question papers

Time: 3 hours Max Marks: 80

Answer any FIVE Questions

All Questions carry equal marks


1. (a) What is the length of the instruction queue in 8086? Discuss the use of the queue? Explain the reason for limiting the length of queue?
(b) What is the minimum number of segment resisters that are necessary to provide segmentation? How do you access common data for different programs using segmentation? [8+8]

2. (a) Distinguish between packed BCD and unpacked BCD
(b) Explain branch instructions of 8086 with examples. [4+12]

3. (a) It is necessary to move a block of data of length 300H from location 6000H:A000H to location 0C000H:B000H. Write an ALP using string instructions to perform the task?
(b) What happens to the SI, DI, and CX registers when the MOVSB instruction is executed (without a repeat prefix) and:
i. the direction flag is set
ii. the direction flag is clear. [8+8]

4. (a) List the signals in minimum and maximum modes.
(b) Explain the roles of pins TEST, LOCK.
(c) Which are the pins of 8086 that are to be connected to interface 8284 and explain their functions? [5+5+6]

5. (a) What do you mean by BSR mode? Explain the BSR mode of operation.
(b) Initialize the Port-A as input port in mode-1. Explain the data transfer scheme used through Port-A with the help of handshaking signals. Draw the timing diagram. [7+9]

6. Write an initialization sequence for an 8259 that is the only 8259 in an 8086 based system, with an even address of 0C0H, that will cause: (a) Request to the edge triggered mode.
(b) IR0 request to an interrupt type-30.
(c) SP/EN to output a disable signal to the data bus transceivers.
(d) The ISR bits to be cleared automatically at the end of second INTA pulse.
(e) The IMR to be cleared.(f) The highest priority interrupt will be IR6.

7. (a) Discuss the mode instruction format of 8251 for synchronous and asynchronous mode of operation.
(b) Discuss overrun error and framing error with reference to 8251. [8+8]

8. Interface Four 8 K Bytes chips of RAM each and Two chips of EPROM each of 4 K bytes with 8051, so that it starts execution in the external program memory and the RAM is mapped at the end of the external data memory address map. Also interface two 8255’s with the 8051 and write an ALP to initialize the 8255 chips with all ports as input ports in mode-0, read all the 8255 ports and store the data read from the 8255 ports in the external data RAM at addresses starting from D000H.

FEEL USEFUL PLEASE GIVE +1