LINEAR AND DIGITAL IC APPLICATONS JNTU previous years question papers

LINEAR AND DIGITAL IC APPLICATONS JNTU previous years question papers

Time: 3 hours Max Marks: 80

Answer any FIVE Questions

All Questions carry equal marks

1. (a) An op-amp has a slew rate of 2V/µs. What is the maximum frequency of an output sinusoid of peak value 5V at which the distortion sets in due to the slew rate limitation. Derive the formulae used.
(b) If the sinusoid of 10V peak is specified, what is the full power band width?
(c) List out the non ideal Dc characteristics of an Op-amp? [8+4+4]

2. (a) Explain HWR using inverting and non-inverting configuration.
(b) Explain the operation of astable multivibrator using Op-amp. [8+8]

3. (a) Draw the schematic diagram of Wien Bridge Oscillator and derive the expression for frequency of oscillation.
(b) What are the conditions to be satisfied by a circuit to produce oscillations?[10+6]

4. (a) Draw the block schematic of a 566 voltage controlled oscillator IC.
(b) Derive an expression for the voltage to frequency conversion factor of 566 VCO. [8+8]

5. (a) Draw the block diagram for a 2-bit parallel-comparator A/D converter and explain the operation of the system.
(b) Draw a schematic diagram of a ladder network D/A converter. Explain the operation of the converter. [8+8]

6. (a) Explain how to estimate sinking current for low output and sourcing current for high output of CMOS gate?
(b) Analyze the fall time of CMOS inverter output with RL = 1K
VL = 2.5V and CL = 100PF. Assume VL as stable state voltage. [8+8]

7. (a) Write short notes on full subtractor?
(b) Give the logic diagram of 74×148 and explain its truth table? [8+8]

8. (a) Design a modulo-100 counter using two 74×163 binary counters?
(b) Design an 8-bit parallel-in and serial-out shift register? Explain the operation of the above shift register with the help of timing waveforms?

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