Anna University Tiruchirappalli - 620 024 Regulations 2007
Sylllabus M.E. COMPUTER SCIENCE AND ENGINEERING
SEMESTER I
CS5101 – COMPUTER ARCHITECTURE
L: 45 T: 15 Total: 60
TEXTBOOK
1. John L. Hennessey and David A. Patterson, “Computer Architecture A Quantitative
Approach”, 3rd Edition, Morgan Kaufmann, 2003.
REFERENCES
1. D. Sima- T. Fountain and P. Kacsuk, “Advanced Computer Architectures A Design Space
Approach”, Addison Wesley, 2000.
2. Kai Hwang, “Advanced Computer Architecture Parallelism Scalability Programmability”,
Tata Mcgraw Hill, 2001.
3. Vincent P. Heuring, Harry F. Jordan, “Computer System Design and Architecture”, 2nd
Edition, Addison Wesley, 2004.
Sylllabus M.E. COMPUTER SCIENCE AND ENGINEERING
SEMESTER I
CS5101 – COMPUTER ARCHITECTURE
UNIT I FUNDAMENTALS OF COMPUTER DESIGN 9
Measuring and Reporting Performance – Quantitative Principles of Computer Design – Classifying Instruction set Architecture – Memory Addressing – Addressing Modes – Type and Size of Operands – Operations in the Instruction Set – Operands and Operations for Media and Signal Processing – Instructions for Control Flow – Encoding an Instruction Set – Example Architecture – MIPS and TM32.
UNIT II INSTRUCTION LEVEL PARALLELISM 9
Pipelining and Hazards – Concepts of ILP – Dynamic Scheduling – Dynamic Hardware Prediction –Multiple Issues – Hardware based Speculation – Limitations of ILP – Case Studies – lP6 Micro Measuring and Reporting Performance – Quantitative Principles of Computer Design – Classifying Instruction set Architecture – Memory Addressing – Addressing Modes – Type and Size of Operands – Operations in the Instruction Set – Operands and Operations for Media and Signal Processing – Instructions for Control Flow – Encoding an Instruction Set – Example Architecture – MIPS and TM32.
UNIT II INSTRUCTION LEVEL PARALLELISM 9
Architecture
UNIT III INSTRUCTION LEVEL PARALLELISM WITH SOFTWARE APPROAC 9
Compiler Techniques for Exposing ILP – Static Branch Prediction – Static Multiple Issue. VLIW –
Advanced Compiler Support – Hardware Support for Exposing Parallelism – Hardware Vs Software Speculation. Mechanism – IA 64 and Itanium Processor.
UNIT IV MEMORY AND I/O 9
Cache Performance – Reducing Cache Miss Penalty and Miss Rate – Reducing Hit Time – Main
Memory and Performance – Memory Technology – Types of Storage Devices – Buses – RAID –
Reliability– Availability and Dependability – I/O Performance Measures – Designing I/O System.
UNIT V MULTIPROCESSORS AND THREAD LEVEL PARALLELISM 9
Symmetric and Distributed Shared Memory Architectures – Performance Issues – Synchronization – Models of Memory Consistency – Multithreading.
UNIT III INSTRUCTION LEVEL PARALLELISM WITH SOFTWARE APPROAC 9
Compiler Techniques for Exposing ILP – Static Branch Prediction – Static Multiple Issue. VLIW –
Advanced Compiler Support – Hardware Support for Exposing Parallelism – Hardware Vs Software Speculation. Mechanism – IA 64 and Itanium Processor.
UNIT IV MEMORY AND I/O 9
Cache Performance – Reducing Cache Miss Penalty and Miss Rate – Reducing Hit Time – Main
Memory and Performance – Memory Technology – Types of Storage Devices – Buses – RAID –
Reliability– Availability and Dependability – I/O Performance Measures – Designing I/O System.
UNIT V MULTIPROCESSORS AND THREAD LEVEL PARALLELISM 9
Symmetric and Distributed Shared Memory Architectures – Performance Issues – Synchronization – Models of Memory Consistency – Multithreading.
L: 45 T: 15 Total: 60
TEXTBOOK
1. John L. Hennessey and David A. Patterson, “Computer Architecture A Quantitative
Approach”, 3rd Edition, Morgan Kaufmann, 2003.
REFERENCES
1. D. Sima- T. Fountain and P. Kacsuk, “Advanced Computer Architectures A Design Space
Approach”, Addison Wesley, 2000.
2. Kai Hwang, “Advanced Computer Architecture Parallelism Scalability Programmability”,
Tata Mcgraw Hill, 2001.
3. Vincent P. Heuring, Harry F. Jordan, “Computer System Design and Architecture”, 2nd
Edition, Addison Wesley, 2004.
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